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? 2013 microchip technology inc. preliminary ds21392a-page 1 features ? single voltage read and write operations - 1.65-1.95v ? serial interface architecture - spi compatible: mode 0 and mode 3 ? high speed clock frequency - 40mhz ? superior reliability - endurance: 100,000 cycles - greater than 20 years data retention ? ultra-low power consumption: - active read current: 4 ma (typical) - standby current: 10 a (typical) - power-down mode standby current: 4 a (typical) ? flexible erase capability - uniform 4 kbyte sectors - uniform 64 kbyte overlay blocks ? page program mode - 256 bytes/page ? fast erase and page-program: - chip-erase time: 300 ms (typical) - sector-erase time: 40 ms (typical) - block-erase time: 80 ms (typical) - page-program time: 3 ms/ 256 bytes (typical) ? end-of-write detection - software polling the busy bit in status register ? hold pin (hold#) - suspend a serial sequence without deselect- ing the device ? write protection (wp#) - enables/disables the lock-down function of the status register ? software write protection - write protection through block-protection bits in status register ? temperature range - industrial: -40c to +85c ? packages available - 8-lead soic (150 mils) - 8-contact uson (2mm x 3mm) ? all devices are rohs compliant product description sst25wf020a is a member of the serial flash 25 series family and feature a four-wire, spi-compatible interface that allows for a low pin-count package which occupies less board space and ultimately lowers total system costs. spi serial fl ash memory is manufactured with proprietary, high-performance cmos superflash technology. the split-gate cell design and thick-oxide tunneling injector attain bet ter reliability and manufac- turability compared with alternate approaches. this serial flash signific antly improve performance and reliability, while lowering power consumption. the device writes (program or erase) with a single power supply of 1.65-1.95v. the total energy consumed is a function of the applied voltage, current, and time of application. since for any given voltage range, the superflash technology uses less current to program and has a shorter erase time, the total energy con- sumed during any erase or program operation is less than alternative flash memory technologies. sst25wf020a is offered in 8-lead soic and 8-contact uson packages. see figure 2-1 for the pin assign- ments. sst25wf020a 2 mbit 1.8v spi serial flash
sst25wf020a ds21392a-page 2 preliminary ? 2013 microchip technology inc. 1.0 functional block diagram figure 1-1: functional block diagram 25139 f01.0 i/o buffers and data latches superflash memory x - decoder control logic address buffers and latches ce# y - decoder sck si so wp# hold# serial interface
? 2013 microchip technology inc. preliminary ds21392a-page 3 sst25wf020a 2.0 pin description figure 2-1: pin assignments table 2-1: pin description symbol pin name functions sck serial clock to provide the input/outp ut timing of the serial interface. commands, addresses, or input data are la tched on the rising edge of the clock input, while output data is shifted out on the falling edge of the clock input. si serial data input to transfer commands, addresses, or data serially into the device. inputs are latched on the rising edge of the serial clock. so serial data output to transfer data serially out of the device. data is shifted out on the falling edge of the serial clock. ce# chip enable the device is enabled by a high to low transition on ce#. ce# must remain low for the duration of any command sequence. the device is deselected and placed in standby mode when ce# is high. wp# write protect the write protect (wp#) pin is us ed to enable/disable bpl bit in the status reg- ister. hold# hold to temporarily stop serial commun ication with spi flash memory while device is selected. v dd power supply to provide power supply voltage: 1.65-1.95v for sst25wf020a v ss ground 8-lead soic 8-contact uson 1 2 3 4 8 7 6 5 ce# so wp# v ss v dd hold# sck si 25139 08-soic-p0.0 1 2 3 4 8 7 6 5 ce# so wp# v ss top v iew v dd hold# sck si 25139 08-uson q3a p1.0
sst25wf020a ds21392a-page 4 preliminary ? 2013 microchip technology inc. 3.0 memory organization the sst25wf020a superflash memory arrays are organized in 64 uniform 4 kbyte sectors, with four 64 kbyte overlay erasable blocks. figure 3-1: memory map 4.0 device operation sst25wf020a is accessed through the spi (serial peripheral interface) bus compatible protocol. the spi bus consist of four control lines; chip enable (ce#) is used to select the device, and data is accessed through the serial data input (si), serial data output (so), and serial clock (sck). the sst25wf020a supports both mode 0 (0,0) and mode 3 (1,1) of spi bus operations. the difference between the two modes, as shown in figure 4-1 , is the state of the sck signal when the bus master is in stand-by mode and no data is being transferred. the sck signal is low for mode 0 and sck signal is high for mode 3. for both modes, the serial data in (si) is sam- pled at the rising edge of the sck clock signal and the serial data output (so) is driven after the falling edge of the sck clock signal. figure 4-1: spi protocol 25139 f51.0 top of memory block 00ffffh 00f000h 000fffh 000000h 001fffh 001000h bottom of memory block . . . 01ffffh 01f000h 01ffffh 010000h . . . . . . 03ffffh 03f000h 030fffh 030000h . . . number of sectors 15 0 1 . . . 31 16 . . . . . . 63 48 . . . 1 0 . . . 3 number of 64 kbyte blocks 25139 f03.0 mode 3 sck si so ce# mode 3 don't care bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mode 0 mode 0 high impedance msb msb
? 2013 microchip technology inc. preliminary ds21392a-page 5 sst25wf020a 4.0.1 hold in the hold mode, serial sequences underway with the spi flash memory are paused without resetting the clocking sequence. to activate the hold# mode, ce# must be in active low state. the hold# mode begins when the sck active low state coincides with the falling edge of the hold# signal. the hold mode ends when the rising edge of the hold# signal coincides with the sck active low state. hold# must not rise or fall when sck logic level is high. see figure 4-2 for hold condi- tion waveform. once the device enters hold mode, so will be in high- impedance state while si and sck can be v il or v ih. if ce# is driven active high during a hold condition, the device returns to standby mode. the device can then be re-initiated with the command sequences listed in table 5-1 . as long as hold# signal is low, the memory remains in the hold conditi on. to resume communica- tion with the device, hold# must be driven active high, and ce# must be driven active low. see figure 4-2 for hold timing. figure 4-2: hold condition waveform 4.1 write protection sst25wf020a provides software write protection. the write protect pin (wp#) enables or disables the lock- down function of the status register. the block-protec- tion bits (bp0, bp1, tb, and bpl) in the status register provide write protection to the memory array and the status register. see table 4-3 for the block-protection description. 4.1.1 write protect pin (wp#) the write protect (wp#) pin enables the lock-down function of the bpl bit (bit 7) in the status register. when wp# is driven low, the execution of the write- status-register (wrsr) instruction is determined by the value of the bpl bit (see table 4-1 ). when wp# is high, the lock-down function of the bpl bit is disabled. active hold active 25139 f05.1 sck hold# table 4-1: conditions to execute write- status-register (wrsr) instruction wp# bpl execute wrsr instruction l 1 not allowed l 0 allowed h x allowed
sst25wf020a ds21392a-page 6 preliminary ? 2013 microchip technology inc. 4.2 status register the software status register provides status on whether the flash memory array is available for any read or write operation, w hether the device is write enabled, and the state of t he memory write protection. during an internal erase or program operation, the sta- tus register may be read only to determine the comple- tion of an operation in progress. table 4-2 describes the function of each bit in t he software status register. 4.2.1 busy (bit 0) the busy bit determines whether there is an internal erase or program operation in progress. a ?1? for the busy bit indicates the device is busy with an operation in progress. a ?0? indicates the device is ready for the next valid operation. 4.2.2 write enable latch (wel?bit 1) the write-enable-latch bit indicates the status of the internal write-enable-latch memory. if the wel bit is set to ?1?, it indicates the device is write enabled. if the bit is set to ?0? (reset), it in dicates the device is not write enabled and does not accept any write (program/ erase) commands. the write- enable-latch bit is auto- matically reset under the following conditions: ? power-up ? write-disable (wrdi) instruction completion ? page-program instruction completion ? sector-erase instruction completion ? 64 kbyte block-erase instruction completion ? chip-erase instruction completion ? write-status-register instruction completion 4.2.3 block-protect ion (bp0, bp1, and tb?bits 2, 3, and 5) the block-protection (bp0, bp1, and tb) bits define the size of the memory area to be software protected against any memory write (program or erase) opera- tion, see table 4-3 . the write-status-register (wrsr) instruction is used to program the bp0, bp1, and tb bits as long as wp# is high or the block-protect-lock (bpl) bit is ?0?. chip-erase can only be executed if block-protection bits are all ?0?. bp0 and bp1 select the protected area and tb alloca tes the protected area to the higher-order address area (top blocks) or lower- order address area (bottom blocks). table 4-2: software status register bit name function default at power-up read/write 0 busy 1 = internal write operation is in progress 0 = no internal write operation is in progress 0r 1 wel 1 = device is memory write enabled 0 = device is not memory write enabled 0r 2 bp0 1 1. bp0, bp1, tb, and bpl bits are non- v olatile memory bits. indicate current level of block write protection (see table 4-3 ) 0 or 1 r/w 3 bp1 1 indicate current level of block write protection (see table 4-3 ) 0 or 1 r/w 4 res reserved for future use 0 n/a 5tb 1 1 = 1/4 or 1/2 bottom memory blocks are protected (see table 4-3 ) 0 = 1/2 or 1/4 top memo ry blocks are protected 0 or 1 r/w 6 res reserved for future use 0 n/a 7 bpl 1 1 = bp0, bp1, tb, and bpl are read-only bits 0 = bp0, bp1, tb, and bpl are read/writable 0 or 1 r/w
? 2013 microchip technology inc. preliminary ds21392a-page 7 sst25wf020a 4.2.4 block protection lock-down (bpl?bit 7) when the wp# pin is driven low (v il ), it enables the block-protection-lock-down (bpl) bit. when bpl is set to ?1?, it prevents any further alteration of the bp0, bp1, tb, and bpl bits. when the wp# pin is driven high (v ih ), the bpl bit has no effect and its value is ?don?t care?. table 4-3: software status register block protection protection level status register bit protected memory address tb bp1 bp0 0 (full memory array unprotected) x00 none t1 (1/4 top memory block protected) 0 0 1 030000h-03ffffh t2 (1/2 top memory block protected) 0 1 0 020000h-03ffffh b1 (1/4 bottom memory block protected) 1 0 1 000000h-00ffffh b2 (1/2 bottom memory block protected) 1 1 0 000000h-01ffffh 3 (full memory array protected) x 1 1 000000h-03ffffh
sst25wf020a ds21392a-page 8 preliminary ? 2013 microchip technology inc. 5.0 instructions instructions are used to read, write (erase and pro- gram), and configure the sst25wf020a devices. the instruction bus cycles are 8 bits each for commands (op code), data, and addresses. the write-enable (wren) instruction must be executed prior to sector- erase, block-erase, page-program, write-status-reg- ister, or chip-erase instructions. the complete instruc- tions are provided in table 5-1 . all instructions are synchronized off a high-to-lo w transition of ce#. inputs will be accepted on the rising edge of sck starting with the most significant bit. ce# must be driven low before an instruction is entered and must be driven high after the last bit of the instruction has been shifted in (except for read, read-id, and read-status-register instruc- tions). any low-to-high transition on ce#, before receiv- ing the last bit of an instru ction bus cycle, will terminate the instruction in progress and return the device to standby mode. instruction commands (op code), addresses, and data are all input from the most signifi- cant bit (msb) first. table 5-1: device operation instructions instruction description op code cycle 1 1. one bus cycle is eight clock periods. address cycle(s) 2 2. address bits abo v e the most significant bi t of each density can be v il or v ih . dummy cycle(s) data cycle(s) maximum frequency read read memory 0000 0011b (03h) 3 0 1 to 25 mhz high-speed read read memory at higher speed 0000 1011b (0bh) 3 1 1 to 40 mhz 4 kbyte sector- erase 3 3. 4 kbyte sector-erase addresses: use a ms -a 12, remaining addresses are don?t care but must be set either at v il or v ih. erase 4 kbyte of memory array 0010 0000b (20h) 1101 0111b (d7h) 300 64 kbyte block- erase 4 4. 64 kbyte block-erase addresses: use a ms -a 16, remaining addresses are don?t care but must be set either at v il or v ih. erase 64 kbyte block of memory array 1101 1000b (d8h) 3 0 0 chip-erase erase full memory array 0110 0000b (60h) or 1100 0111b (c7h) 000 page-program to program up to 256 bytes 0000 0010b (02h) 3 0 1 to 256 rdsr 5 5. the read-status-register is continuous w ith ongoing clock cycles until terminated by a lo w to high transition on ce#. read-status-register 0000 0101b (05h) 0 0 1 to wrsr write-status-register 0000 0001b (01h) 0 0 1 wren write-enable 0000 0110b (06h) 0 0 0 wrdi write-disable 0000 0100b (04h) 0 0 0 rdid 6, 7 6. de v ice id is read after three dummy address bytes. the de v ice id output stream is continuous until terminated by a lo w -to- high transition on ce#. 7. the instructions release from deep po w er do w n and read-id are similar instructions (abh). executing read-id requires the abh instruction, follo w ed by 24 dummy address bits to retrie v e the de v ice id. release from deep po w er-do wn only requires the instruction abh. read-id 1010 1011b (abh) 3 0 1 to jedec-id jedec id read 1001 1111b (9fh) 0 0 4 to dpd deep power-down mode 1011 1001b (b9h) 0 0 0 rdpd 7 release from deep power- down or read id 1010 1011b (abh) 0 0 0
? 2013 microchip technology inc. preliminary ds21392a-page 9 sst25wf020a 5.1 read (25 mhz) the read instruction, 03h, supports up to 25 mhz read. the device outputs a data stream starting from the specified address location. the data stream is con- tinuous through all addresses until terminated by a low- to-high transition on ce#. the internal address pointer automatically increments until the highest memory address is reached. once the highest memory address is reached, the address pointer automatically incre- ments to the beginning (wrap-around) of the address space. for example, for 2 mbit density, once the data from the address location 3ffffh is read, the next out- put is from address location 000000h. the read instruction is initiated by executing an 8-bit command, 03h, followed by address bits a 23 -a 0 . ce# must remain active low for the duration of the read cycle. see figure 5-1 for the read sequence. figure 5-1: read sequence 5.2 high-speed-read (40 mhz) the high-speed-read instruction supporting up to 40 mhz read is initiated by executing an 8-bit command, 0bh, followed by address bits [a 23 -a 0 ] and a dummy byte. ce# must remain active low for the duration of the high-speed-read cycle. see figure 5-2 for the high- speed-read sequence. following a dummy cycle, the high-speed-read instruction outputs the data starting from the specified address location. the data output stream is continuous through all addresses until terminated by a low-to-high transition on ce#. the internal address pointer will automatically increment until the highest memory address is reached. once the highest memory address is reached, the address pointer will automatically incre- ment to the beginning (wr ap-around) of the address space. for example, for 2 mbit density, once the data from address location 3fff fh is read, the next output will be from address location 000000h. figure 5-2: high-speed-read sequence 25139 f06.0 ce# so si sck add. 012345678 add. add. 03 high impedance 15 16 23 24 31 32 39 40 70 47 48 55 56 63 64 n+2 n+3 n+4 n n+1 d out msb msb msb mode 0 mode 3 d out d out d out d out 25139 f07.0 ce# so si sck add. 012345678 add. add. 0b high impedance 15 16 23 24 31 32 39 40 47 48 55 56 63 64 n+2 n+3 n+4 n n+1 x msb mode 0 mode 3 d out d out d out d out 80 71 72 d out msb
sst25wf020a ds21392a-page 10 preliminary ? 2013 microchip technology inc. 5.3 page-program the page-program instruction programs up to 256 bytes of data in the memory. the data for the selected page address must be in the erased state (ffh) before initiating the page-program operation. a page-pro- gram applied to a protected memory area will be ignored. prior to the prog ram operation, execute the wren instruction. to execute a page-program operation, the host drives ce# low, then sends the page-program command cycle (02h), three address cycles, followed by the data to be programmed, and then drives ce# high. the pro- grammed data must be between 1 to 256 bytes and in whole byte increments; sending less than a full byte will cause the partial byte to be ignored. poll the busy bit in the status register, or wait t pp , for the completion of the internal, self-timed, page-program operation. see figure 5-3 for the page-program sequence and figure 6-8 for the page-program flow chart. when executing page-program, the memory range for the sst25wf020a is divided into 256-byte page boundaries. the device handles the shifting of more than 256 bytes of data by maintaining the last 256 bytes as the correct data to be programmed. if the tar- get address for the page-program instruction is not the beginning of the page boundary (a[7:0] are not all zero), and the number of bytes of data input exceeds or overlaps the end of the address of the page boundary, the excess data inputs wrap around and will be pro- grammed at the start of that target page. figure 5-3: page-program sequence 25139 f60.1 ce# so si sck add. 01234567 8 add. add. data byte 0 02 high impeda nce 15 16 23 24 31 32 39 mode 0 mode 3 msb msb msb lsb ce# (cont?) so (cont?) si (cont?) sck (cont?) 40 41 42 43 44 45 46 47 4 8 data byte 1 high impeda nce msb msb msb lsb 50 51 52 53 54 55 2072 49 data byte 2 2073 2074 2075 2076 2077 2078 2079 data byte 255 lsb lsb lsb lsb
? 2013 microchip technology inc. preliminary ds21392a-page 11 sst25wf020a 5.4 sector-erase the sector-erase instructio n clears all bits in the selected 4 kbyte sector to ffh. a sector-erase instruction applied to a protected memory area will be ignored. prior to any write operation, the write-enable (wren) instruction must be executed. ce# must remain active low for the duration of any command sequence. the sector-erase instruction is initiated by executing an 8-bit command, 20h or d7h, followed by address bits [a 23 -a 0 ]. address bits [a ms -a 12 ] (a ms = most significant addre ss) are used to deter- mine the sector address (sa x ), remaining address bits can be v il or v ih. ce# must be driven high before the instruction is executed. poll the busy bit in the soft- ware status register, or wait t se , for the completion of the internal self-timed sector-erase cycle. see figure 5-4 for the sector-erase sequence and figure 6-9 for the flow chart. figure 5-4: sector-erase sequence 5.5 64-kbyte block-erase the 64-kbyte block-erase instruction clears all bits in the selected 64 kbyte block to ffh. applying this instruction to a protected memory area results in the instruction being ignored. prior to any write operation, the write-enable (wren) instruction must be executed. ce# must remain active low for the duration of any com- mand sequence. initiate the 64-byte block-er ase instruction by execut- ing an 8-bit command, d8h, followed by address bits [a 23 -a 0 ]. address bits [a ms -a 16 ] (a ms = most signifi- cant address) determine the block address (ba x ), remaining address bits can be v il or v ih. ce# must be driven high before executing th e instruction. poll the busy bit in the software status register or wait t be for the com- pletion of the internal self -timed block-erase cycle. see figure 5-5 for the 64-kbyte block-erase sequences and figure 6-9 for the flow chart. figure 5-5: 64-kbyte block-erase sequence ce# so si sck add. 012345678 add. add. 20 or d7 high impedance 15 16 23 24 31 mode 0 mode 3 2539 f13.0 msb msb ce# so si sck addr 012345678 addr addr d8 high impedance 15 16 23 24 31 mode 0 mode 3 25139 f15.0 msb msb
sst25wf020a ds21392a-page 12 preliminary ? 2013 microchip technology inc. 5.6 chip-erase the chip-erase instruction clears all bits in the device to ffh. a chip-erase instruction is ignored if any of the memory area is protected. prior to any write operation, the write-enable (wren) instruction must be executed. ce# must remain active low for the duration of the chip-erase instruction sequence. initiate the chip- erase instruction by executing an 8-bit command, 60h or c7h. ce# must be driven high before the instruction is executed. poll the busy bit in the software status reg- ister, or wait t ce , for the completion of the internal self- timed chip-erase cycle. see figure 5-6 for the chip- erase sequence and figure 6-10 for the flow chart. figure 5-6: chip-erase sequence 5.7 read-status-register (rdsr) the read-status-register (rdsr) instruction, 05h, allows reading of the status register. the status register may be read at any time even during a write (program/ erase) operation. when a write operation is in prog- ress, the busy bit may be checked before sending any new commands to assure that the new commands are properly received by the device. ce# must be driven low before the rdsr instruction is entered and remain low until the status data is read. read-status-register is continuous with ongoing clock cycles until it is termi- nated by a low to high transition of the ce#. see figure 5-7 for the rdsr instruction sequence. figure 5-7: read-status-register (rdsr) sequence ce# so si sck 01234567 60 or c7 high impedance mode 0 mode 3 25139 f16.0 msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 25139 f17.0 mode 3 sck si so ce# bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 05 mode 0 high impedance status register out msb msb
? 2013 microchip technology inc. preliminary ds21392a-page 13 sst25wf020a 5.8 write-enable (wren) the write-enable (wren) instruction, 06h, sets the write-enable-latch bit in the status register to 1 allow- ing write operations to occur. the wren instruction must be executed prior to any write (program/erase) operation. the wren instruction may also be used to allow execution of the write-status-register (wrsr) instruction; however, the write-enable-latch bit in the status register will be cleared upon the rising edge ce# of the wrsr instruction. ce# must be driven low before entering the wren instruction, and ce# must be driven high before executing the wren instruction. see figure 5-8 for the wren instruction sequence. figure 5-8: write enable (wren) sequence 5.9 write-disable (wrdi) the write-disable (wrdi) inst ruction, 04h, resets the write-enable-latch bit to ?0?, thus preventing any new write operations. ce# must be driven low before enter- ing the wrdi instruction, and ce# must be driven high before executing the wrdi instruction. see figure 5-11 for the wrdi instruction sequence. figure 5-9: write disable (wrdi) sequence ce# so si sck 01234567 06 high impedance mode 0 mode 3 25139 f18.0 msb ce# so si sck 01234567 04 high impedance mode 0 mode 3 25139 f19.0 msb
sst25wf020a ds21392a-page 14 preliminary ? 2013 microchip technology inc. 5.10 write-status-register (wrsr) the write-status-register in struction writes new val- ues to the bp0, bp1, tb, and bpl bits of the status reg- ister. ce# must be driven low before the command sequence of the wrsr instruction is entered and driven high before the wrsr instruction is executed. poll the busy bit in the software status register, or wait t wrsr , for the completion of the internal self-timed write-status-register cycle. see figure 5-10 for wren and wrsr instruction sequences and figure 6- 11 for the wrsr flow chart. executing the write-status-r egister instruction will be ignored when wp# is low and bpl bit is set to ?1?. when the wp# is low, the bpl bit can only be set from ?0? to ?1? to lock-down the status register, but cannot be reset from ?1? to ?0?. when wp# is high, the lock-down func- tion of the bpl bit is disabled and the bpl, bp0, bp1, and tb bits in the status register can all be changed. as long as bpl bit is set to ?0? or wp# pin is driven high (v ih ) prior to the low-to-high transition of the ce# pin at the end of the wrsr instruct ion, the bits in the status register can all be altered by the wrsr instruction. in this case, a single wrsr instruction can set the bpl bit to ?1? to lock down the status register as well as alter- ing the bp0, bp1, and tb bits at the same time. see table 4-1 for a summary description of wp# and bpl functions. figure 5-10: write-enable (wren) and write-status-register (wrsr) sequence 25139 f20.0 mode 3 high impedance mode 0 status register in 76543210 msb msb msb 01 mode 3 sck si so ce# mode 0 06 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
? 2013 microchip technology inc. preliminary ds21392a-page 15 sst25wf020a 5.11 power-down the deep power-down (dpd) instruction puts the device in the lowest power consumption mode ? the deep power-down mode. this instruction is ignored if the device is busy with an internal write operation. while the device is in dpd mode, all instructions are ignored except for the release deep power-down instruction or read id. to initiate deep power-down, input the deep power- down instruction (b9h) while driving ce# low. ce# must be driven high before executing the dpd instruc- tion. after driving ce# high, it requires a delay of t dpd before the standby current i sb is reduced to the deep power-down current i dpd . see figure 5-11 for the dpd instruction sequence. exit the power-down state using the release from deep power-down or read id instruction. ce# must be driven low before sending the release from deep power-down command cycle (abh), and then driving ce# high. the device will return to standby mode and be ready for the next instruction after t sbr . see figure 5-12 . for the release from deep power-down sequence. figure 5-11: deep power-down sequence figure 5-12: release from deep power-down sequence ce# so si sck 01234567 b9 high impeda nce mode 0 mode 3 25139 f46.1 msb t dpd ce# so si sck 01234567 ab high impeda nce mode 0 mode 3 25139 f47.1 msb t sbr
sst25wf020a ds21392a-page 16 preliminary ? 2013 microchip technology inc. 5.12 read-id the read-id instruction identifies the device as sst25wf020a. use the read-id instruction to identify sst25wf020a when using multiple manufacturers in the same socket. see table 5-2 . the device id information is read by executing an 8-bit command, abh, followed by 24 dummy address bits. following the read-id instruction, and 24 address dummy bits, the device id continues to output with con- tinuous clock input until terminated by a low-to-high transition on ce#. figure 5-13: read-id sequence 5.13 jedec read-id the jedec read-id instruction identifies the device id information of sst25wf020a. the device information can be read by executing the 8-bit command, 9fh. fol- lowing the jedec read-id instruction, a 32bit device id information is output from the device. the device id information is assigned by the manufacturer and con- tains the device id 1 in the first byte, the type of mem- ory in the second byte, the memory capacity of the device in the third byte, and a reserved code in the fourth byte. the 4-byte code outputs repeatedly with continuous clock input until a low-to-high transition on ce#. see figure 5-14 for the instruction sequence. the jedec read id instruction is terminated by a low to high transition on ce# at any time during data output. figure 5-14: jedec read-id sequence table 5-2: product identification address data sst25wf020a id xxxxxxh 34h 25139 f22.1 ce# so si sck xx 01234567 8 xx xx ab high impeda nce 15 16 23 24 31 32 39 40 47 4 8 55 56 63 device id device id high impeda nce mode 3 mode 0 msb msb msb device id device id note: the device id output stream is continuous unti l terminated by a low-to-high transition on ce#. table 5-3: jedec read-id data-out product device id device id 1 (byte 1) memory type (byte 2) memory capacity (byte 3) reserved code (byte 4) sst25wf020a 62h 16h 12h 00h 16 12 00 25139 f23.1 ce# so si sck 012345678 high impeda nce 15 1614 28 29 30 31 62 mode 3 mode 0 msb msb 9 10111213 171 8 32 34 9f 19 20 21 22 23 33 24 25 26 27 37 3 8 39 35 36
? 2013 microchip technology inc. preliminary ds21392a-page 17 sst25wf020a 6.0 electrical specifications absolute maximum stress ratings (applied conditions greater than those listed under ?absolute maxi- mum stress ratings? may cause permanent damage to the de v ice. this is a stress rating only and func- tional operation of the de v ice at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. exposure to absolute maximum stress rating conditions may affect de v ice reliability.) temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55c to +125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 c to +150c d. c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5v to v dd +0.5v transient voltage (<20 ns) on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . .-2.0v to v dd +2.0v package po w er dissipation capability (t a = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0w surface mount solder reflo w temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260c for 10 seconds output short circuit current 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma 1. output shorted for no more than one second. no more than one output shorted at a time. table 6-1: operating range range ambient temp v dd industrial -40c to +85c 1.65-1.95v table 6-2: ac conditions of test input rise/fall time output load 5ns c l = 30 pf
sst25wf020a ds21392a-page 18 preliminary ? 2013 microchip technology inc. 6.1 power-up specifications all functionalities and dc sp ecifications are specified for a v dd ramp rate of greater than 1v per 100 ms (0v to 1.8v in less than 180 ms). see table 6-3 and figure 6-2 for more information. figure 6-1: power-up timing diagram table 6-3: recommended system power-up timings symbol parameter minimum units t pu-read 1 1. this parameter is measured only for initial qualification and after a design or process change that could affect this paramet er. v dd min to read operation 100 s t pu-write 1 v dd min to write operation 100 s time v dd min v dd max v dd de v ice fully accessible t pu-read t pu-write chip selection is not allo w ed. commands may not be accepted or properly interpreted by the de v ice. 25139 f27.0
? 2013 microchip technology inc. preliminary ds21392a-page 19 sst25wf020a 6.2 hardware data protection sst25wf020a provides a power-up reset function. to ensure that the power reset circuit will operate cor- rectly, the device must meet the conditions shown in figure 6-2 and table 6-4 . microchip does not guaran- tee the data in the event of an instantaneous power fail- ure that occurs during a write operation. figure 6-2: power-down timing diagram 6.3 software data protection sst25wf020a prevents unint entional operations by not recognizing commands under the following condi- tions: ? after inputting a write command, if the rising ce# edge timing is not in a bus cycle (8 clk units of sck) ? when the page-program data is not in 1-byte increments ? if the write status register instruction is input for two bus cycles or more. 6.4 decoupling capacitor a 0.1f ceramic capacitor mu st be provided to each device and connected between v dd and v ss to ensure that the device will operate correctly. table 6-4: recommended system power-down timings symbol parameter min max units t pd power-down time 10 ms v bot power-down voltage 0.2 v t pd v dd min v dd max v dd 25139 f48.0 0v v bot
sst25wf020a ds21392a-page 20 preliminary ? 2013 microchip technology inc. 6.5 dc characteristics table 6-5: dc operating characteristics symbol parameter limits test conditions min typ 1 1. value characterized, not fully tested in production. max units i ddr read current 6 ma ce#=0.1 v dd /0.9 v dd @25 mhz, so=open i ddr2 read current 8 ma ce#=0.1 v dd /0.9v dd @40 mhz, so=open i ddw program and erase current 15 ma ce#=v dd i sb standby current 50 a ce#=v dd , v in =v dd or v ss i dpd deep power-down 10 a ce#=v dd , v in =v dd or v ss i li input leakage current 2 a v in =gnd to v dd , v dd =v dd max i lo output leakage current 2 a v out =gnd to v dd , v dd =v dd max v il input low voltage -0.3 0.3 v v dd =v dd min v ih input high voltage 0.7 v dd v dd +0.3 v v dd =v dd max v ol output low voltage 0.2 v i ol =100 a, v dd =v dd min v oh output high voltage v dd -0.2 v i oh =-100 a, v dd =v dd min table 6-6: capacitance (t a = 25c, f=1 mhz, other pins open) parameter description test condition maximum c out 1 1. this parameter is measured only for in itial qualification and after a design or pr ocess change that could affect this paramet er. output pin capacitance v out = 0v 12 pf c in 1 input capacitance v in = 0v 6 pf table 6-7: reliability characteristics symbol parameter minimum specification units test method n end 1 1. this parameter is measured only for in itial qualification and after a design or pr ocess change that could affect this paramet er. endurance 100,000 cycles jedec standard a117 status register write cycle 100,000 cycles jedec standard a117 t dr 1 data retention 20 years jedec standard a103 i lth 1 latch up 100 + i dd ma jedec standard 78
? 2013 microchip technology inc. preliminary ds21392a-page 21 sst25wf020a 6.6 ac characteristics table 6-8: ac operating characteristics symbol parameter limits - 25 mhz limits - 40 mhz units min typ max min typ max f clk 1 1. maximum clock frequency for read instruction, 03h, is 25 mhz serial clock frequency 25 40 mhz t sckh serial clock high time 14 11.5 ns t sckl serial clock low time 14 11.5 ns t sckr serial clock rise time 5 5 ns t sckf serial clock fall time 5 5 ns t ces 2 2. relati v e to sck ce# active setup time 10 10 ns t ceh 2 ce# active hold time 10 10 ns t chs 2 ce# not active setup time 10 10 ns t chh 2 ce# not active hold time 10 10 ns t cph ce# high time 25 25 ns t chz ce# high to high-z output 15 15 ns t clz sck low to low-z output 0 0 ns t ds data in setup time 5 5 ns t dh data in hold time 5 5 ns t hls hold# low setup time 5 5 ns t hhs hold# high setup time 5 5 ns t hlh hold# low hold time 5 5 ns t hhh hold# high hold time 5 5 ns t hz hold# low to high-z output 9 9 ns t lz hold# high to low-z output 12 12 ns t oh output hold from sck change 1 1 ns t v output valid from sck 8 11 8 11 ns t wps wp# setup time 20 20 ns t wph wp# hold time 20 20 ns t wrsr status register write time 10 10 ms t dpd ce# high to deep power-down 5 5 s t sbr deep power-down (ce# high) to standby mode 5 5s t se sector-erase 40 150 40 150 ms t be block-erase 80 250 80 250 ms t ce chip-erase 0.3 3 0.3 3 s t pp page-program (256 byte) 3.0 3.5 3.0 3.5 ms n byte n byte 0.15 + n*2.85/ 256 0.20 + n*3.30/ 256 n byte 0.15 + n*2.85/ 256 0.20 + n*3.30/ 256 ms
sst25wf020a ds21392a-page 22 preliminary ? 2013 microchip technology inc. figure 6-3: serial input timing diagram figure 6-4: serial output timing diagram figure 6-5: hold timing diagram high-z high-z ce# so si sck msb lsb t ds t dh t chh t ces t ceh t chs t sckr t sckf t cph 25139 f24.0 25139 f25.0 ce# si so sck msb t clz t v t sckh t chz t oh t sckl lsb t hz t lz t hhh t hls t hlh t hhs 25139 f26.1 hold# ce# sck so si t hlh
? 2013 microchip technology inc. preliminary ds21392a-page 23 sst25wf020a figure 6-6: status register write timing figure 6-7: ac input/output reference waveforms 25139 f49.0 t wps t wph ce# wp# 25139 f28.0 reference points output input v ht v lt v ht v lt v iht v ilt ac test inputs are driven at v iht (0.8v dd ) for a logic ?1? and v ilt (0.2v dd ) for a logic ?0?. measurement reference points for inputs and outputs are v ht (0.6v dd ) and v lt (0.4v dd ). input rise and fall times (10% ? 90%) are <5 ns. note: v ht - v high te s t v lt - v low te s t v iht - v input high test v ilt - v input low test
sst25wf020a ds21392a-page 24 preliminary ? 2013 microchip technology inc. figure 6-8: page-program flow chart 25139 f41.1 06h ye s no start 02h address 1 address 2 address 3 data 0 data 255 05h start program on rising edge of ce# bu sy (bit 0) = ?0?? end of programming w rite enab le page program sequence status register read command check program completion ? ? ?
? 2013 microchip technology inc. preliminary ds21392a-page 25 sst25wf020a figure 6-9: sector-erase or 64-kbyte block-erase flow chart 25139 f42.1 06h ye s no start 20h/d7 or d8h address 1 address 2 address 3 05h start erase on rising edge of ce# bu sy (bit 0) = ?0?? end of erase w rite enab le sector-erase (20h/d7h) or 64-kbyte block-erase (d 8h) sequence status register read command check erase completion
sst25wf020a ds21392a-page 26 preliminary ? 2013 microchip technology inc. figure 6-10: chip-erase flow chart 25139 f44.1 06h ye s no start 60h/c7h 05h start erase on rising edge of ce# bu sy (bit 0) = ?0?? end of erase w rite enab le chip-erase status register read command check erase completion
? 2013 microchip technology inc. preliminary ds21392a-page 27 sst25wf020a figure 6-11: write-status- register (wrsr) flow chart 25139 f45.1 06h ye s no start 01h data 05h start w rite on rising edge of ce# bu sy (bit 0) = ?0?? end w rite- status-register w rite enab le w rite-status- register sequence status register read command check w rite completion
sst25wf020a ds21392a-page 28 preliminary ? 2013 microchip technology inc. 7.0 product iden tification system to order or obtain information, e.g., on pricing or deli very, refer to the factory or the listed sales office. part no. xxx xx endurance/ operating device device: sst25wf020a = 2 mbit,1.65-1.95v, serial flash memory tape and reel flag: t = tape and reel operating frequency: 40 = 40 mhz endurance: 5 = 100,000 cycles temperature: i = -40c to +85c package: np = uson (2mm x 3mm body), 8-contact sn = soic (150 mil body), 8-lead valid combinations: sst25wf020at-40-5i-np sst25wf020a-40-5i-sn SST25WF020AT-40-5I-SN x tape/reel indicator frequency xx package temperature
? 2013 microchip technology inc. preliminary ds21392a-page 29 sst25wf020a 8.0 packaging diagrams note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
sst25wf020a ds21392a-page 30 preliminary ? 2013 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2013 microchip technology inc. preliminary ds21392a-page 31 sst25wf020a
sst25wf020a ds21392a-page 32 preliminary ? 2013 microchip technology inc.
? 2013 microchip technology inc. preliminary ds21392a-page 33 sst25wf020a table 8-1: revision history revision ? description date a ? initial release of data sheet feb 2013
sst25wf020a ds21392a-page 34 preliminary ? 2013 microchip technology inc. the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faqs), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under ?support?, click on ?customer change notification? and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support ? development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sa les offices and locations is included in the back of this document. technical support is available through the web site at: http://microchip.com/support
? 2013 microchip technology inc. preliminary ds21392a-page 35 information contained in this publication regarding device applications and the like is prov ided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application me ets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safe ty applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting fr om such use. no licenses are conveyed, implicitly or ot herwise, under any microchip intellectual property rights. trademarks the microchip name and logo, th e microchip logo, dspic, flashflex, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mtp, seeval and the embedded control solutions company are registered tradema rks of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. analog-for-the-digital age, a pplication maestro, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, sqi, serial quad i/o, total endurance, tsharc, uniwindriver, wiperlock, zena and z-scale are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. gestic and ulpp are registered trademarks of microchip technology germany ii gmbh & co. & kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2013, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 978-1-62077-026-9 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip products in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperi pherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 ==
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